Reliability in Power Electronics and Power Systems

L'abstract è presente nell'allegato / the abstract is in the attachmen

Assessing the effectiveness of different test approaches for power devices in a PCB

Power electronic systems employing Printed Circuit Boards (PCBs) are broadly used in many applications, including some safety-critical ones. Several standards (e.g., ISO26262 for the automotive sector and DO-178 for avionics) mandate the adoption of effective test procedures for all electronic systems. However, the metrics to be used to compute the effectiveness of the adopted test procedures are not so clearly defined for power devices and systems. In the last years, some commercial fault simulation tools (e.g., DefectSim by Mentor Graphics and TestMAX by Synopsys) for analog circuits have been introduced, together with some new fault models. With these new tools, systematic analog fault simulation finally became practically feasible. The aim of this paper is twofold: first, we propose a method to extend the usage of the new analog fault models to power devices, thus allowing to compute a Fault Coverage figure for a given test. Secondly, we adopt the method on a case study, for which we quantitatively evaluate the effectiveness of some test procedures commonly used at the PCB level for the detection of faults inside power devices. A typical Power Supply Unit (PSU) used in industrial products, including power transistors and power diodes, is considered. The analysis of the gathered results shows that using the new method we can identify the main points of strength / weakness of the different test solutions in a quantitative and deterministic manner, and pinpoint the faults escaping to each one

Multilevel Simulation Methodology for FMECA Study Applied to a Complex Cyber-Physical System

Complex systems are composed of numerous interconnected subsystems, each designed to perform specific functions. The different subsystems use many technological items that work together, as for the case of cyber-physical systems. Typically, a cyber-physical system is composed of different mechanical actuators driven by electrical power devices and monitored by sensors. Several approaches are available for designing and validating complex systems, and among them, behavioral-level modeling is becoming one of the most popular. When such cyber-physical systems are employed in mission- or safety-critical applications, it is mandatory to understand the impacts of faults on them and how failures in subsystems can propagate through the overall system. In this paper, we propose a methodology for supporting the failure mode, effects, and criticality analysis (FMECA) aimed at identifying the critical faults and assessing their effects on the overall system. The end goal is to analyze how a fault affecting a single subsystem possibly propagates through the whole cyber-physical system, considering also the embedded software and the mechanical elements. In particular, our approach allows the analysis of the propagation through the whole system (working at high level) of a fault injected at low level. This paper provides a solution to automate the FMECA process (until now mainly performed manually) for complex cyber-physical systems. It improves the failure classification effectiveness: considering our test case, it reduced the number of critical faults from 10 to 6. The remaining four faults are mitigated by the cyber-physical system architecture. The proposed approach has been tested on a real cyber-physical system in charge of driving a three-phase motor for industrial compressors, showing its feasibility and effectiveness

A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips

Modern System-on-Chips (SoCs) deployed for safety-critical applications typically embed one or more processing cores along with a variable number of peripherals. The compliance of such designs with functional safety standards is achieved by a combination of different techniques based on hardware redundancy and in-field test mechanisms. Among these, Software Test Libraries (STLs) are rapidly becoming adopted for testing the CPU and peripherals modules. The STL is usually composed of two sets of self-test procedures: boot-time and run-time tests. The former set is typically executed during the boot or power-on phase of the SoC since it requires full access to the available hardware (e.g., these programs need to manipulate the Interrupt Vector Table and to access the system RAM). The latter set instead, is designed to coexist with the user application and can be executed without requiring special constraints. When the STL is intended for testing the different cores within a multi-core SoC, the concurrent execution of the boot-time self-tests becomes an issue since this could lead to a longer power-up phase and excessive utilization of system resources. The main intent of this work is to present the architecture of a decentralized software scheduler, conceived for the concurrent execution of the STL on the available cores. The proposed solution considers the typical constraints of an STL in a multi-core scenario when deployed in field, namely minimum system resources usage (i.e., code and data memory). The effectiveness of the proposed scheduler was experimentally evaluated on an industrial STL developed for a multi-core SoC manufactured by STMicroelectronics

Test Solution for Heatsinks in Power Electronics Applications

Power electronics technology is widely used in several areas, such as in the railways, automotive, electric vehicles, and renewable energy sectors. Some of these applications are safety critical, e.g., in the automotive domain. The heat produced by power devices must be eciently dissipated to allow them to work within their operational thermal limits. Moreover, numerous ageing eects are due to thermal stress, which causes mechanical issues. Therefore, the reliability of a circuit depends on its dissipation system, even if it consists of a simple passive heatsink mounted on the power device. During the Printed Circuit Board (PCB) production, an incorrect assembly of the heatsink can cause a worse heat dissipation with a significant increase of the junction temperatures (Tj). In this paper, three possible test strategies are compared for testing the correct assembling of heatsinks. The considered strategies are used at the PCB end-manufacturing. The eectiveness of the dierent test methods considered is assessed on a case study corresponding to a Power Supply Unit (PSU)

Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips

Traditionally, the usage of caches and deterministic execution of on-line self-test procedures have been considered two mutually exclusive concepts. At the same time, software executed in a multi-core context suffers of a limited timing predictability due to the higher system bus contention. When dealing with selftest procedures, this higher contention might lead to a fluctuating fault coverage or even the failure of some test programs. This paper presents a cache-based strategy for achieving both deterministic behaviour and stable fault coverage from the execution of self-test procedures in multi-core systems. The proposed strategy is applied to two representative modules negatively affected by a multi-core execution: synchronous imprecise interrupts logic and pipeline hazard detection unit. The experiments illustrate that it is possible to achieve a stable execution while also improving the state-of-the-art approaches for the on-line testing of embedded microprocessors. The effectiveness of the methodology was assessed on all the three cores of a multi-core industrial System- on-Chip intended for automotive ASIL D applications

Assessing Test Procedure Effectiveness for Power Devices

The use of power electronics in safety-critical applications requires specific test techniques for these devices. In particular, it is important to adopt some metric for assessing the quality of a given Test Procedure, e.g., by introducing fault models allowing to compute a Fault Coverage (FC) figure for the analog electronics, as already successfully done for digital electronics. In the digital domain the scientific and industrial community has adopted some fault models (e.g., stuck-at) for permanent faults. The use of this model (and others) allows to establish a priori a finite list of possible faults to be considered, to study their effects during the test (i.e., to determine which of these faults are detected) and during the operational phase (e.g., to perform FMEA), and to generate suitable test procedures targeting them. In the analog domain such widely accepted fault models do not exist, although some fault models have been recently proposed and new commercial tools have been introduced to assess the analog fault coverage. The goal of this paper is to focus on power devices and use a possible fault model for analog and mixed-signal circuits resorting to the device equivalent model for evaluating the Power Fault Coverage (PFC) achieved by a test procedure for the Power Device Under Test (PDUT)

A Possible Strategy for the Development of Software Test Libraries for different Processors of the same Family

In the automotive safety-critical application numerous test solutions are adopted; in particular, different solutions are implemented for the in-field and on-line testing. The Built-In Self-Test (BIST) approach and the Software-Based Self- Test (SBST) approach are two possible test strategies widely used to test the modern processors. The BIST approach is easily reproducible on different processors; while the SBST approach requires a considerable effort for implementing it for each different processor. This paper faces the problem of developing multiple Software Test Libraries (STL) for the processors belonging to the same processor family. The aim of this work is to propose a methodology for planning the test programs develop considering the different processors of the same family. In particular, the different features of the processors are considered. The common features present in all processors, the common features available only in some processors, and the features of just one processor are used for planning the development of the STLs. Each test program is developed in modular way, in accord with the SBST paradigm. The SPC58 processor family developed by STMicroelectronics is considered as case study. The experimental results demonstrate the validity of the proposed approach